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EEE 102

Digital Logic Design

Number systems and conversions, data representation, analysis and design of combinational logic circuits, Boolean algebra, logic gates, minimization techniques, HDL, sequential logic, flip-flops, registers, clocked circuits, clock generation, counters, shift registers, arithmetic circuits.

Credit4
ECTS6.5
BölümElectrical and Electronics Engineering
FacultyFaculty of Engineering
PrereqCS 101 or CS 115
MüfredatY1 Bahar

Hocalar 1 bu dönem · 13 geçmiş

Bu dönem (2025-2026 Spring) · 3 section
Ergin Atalar ×3
Geçmişte ders veren (13 kişi)
Süleyman Serdar Kozat, Cem Tekin, Mustafa Sanlı, Volkan Kurşun, Mehmet Alper Kutay, Erdem Ulusoy, Ruşen Öktem, Heba Yüksel, Yusuf Ziya İder, Murat Eskiyerli, Levent Öktem, Ali Bozbey, M. Erol Sezer

→ STARS müfredatı / syllabus

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Geçmiş GPA dağılımı 35 dönem · ort. 2.28

DönemCourse CPA
2025-2026 Fall 2.04 2 sec · 89 öğr
2024-2025 Fall 2.28 2 sec · 103 öğr
2024-2025 Spring 2.20 3 sec · 177 öğr
2023-2024 Fall 2.48 3 sec · 158 öğr
2023-2024 Spring 2.51 4 sec · 222 öğr
2022-2023 Fall 2.47 3 sec · 147 öğr
2022-2023 Spring 1.77 2 sec · 70 öğr
2021-2022 Fall 2.41 6 sec · 145 öğr
2020-2021 Fall 2.13 3 sec · 167 öğr
2020-2021 Spring 2.57 4 sec · 85 öğr

Aggregate course GPA — Bilkent STARS'tan public data. Hoca-bazlı per-section detayı için STARS evaluation report →. Öğrenci anket cevapları KVKK kapsamında defter'de tutulmaz.

Müfredat detayı STARS syllabus

📚 Önerilen kaynaklar

  • Zorunlu Fundamentals of Digital Logic with VHDL Design Stephen Brown and Zvonko Vranesic · Fourth Edition · McGraw-HIll
  • Önerilen Logic and Computer Design Fundamentals M.M. Mano and C. R. Kime, Prentice Hall
  • Önerilen Digital Design Principles and Practices John F. Wakerly, Pearson Prentice Hall

⚖️ Değerlendirme

  • 35% — Final:Essay/written: Final (×1)
  • 30% — Midterm:Essay/written: Midterm (×1)
  • 16% — Term project: Term project (×1)
  • 14% — Lab work: Lab (×1)
  • 0% — Quiz: Online Quizzes (×1)
  • 5% — In-class attendance: Attendance (×1)

⚠️ FZ engelleyen şartlar

Students should 1) obtain non-zero grade from each of the project presentations and labs AND 2) Collect at least 20/49 from midterm + lab work + quiz + attendance AND 3) attend at least 29 lectures AND 4) obtain no disciplinary penalty related with this course.

📅 Haftalık müfredat

Digital Information. Number Systems. Number system conversions. Simple logic gates. Truth table. Boolean algebra. Canonical design. Bubble-to-bubble logic. Simple logic gates. Truth table. Boolean algebra. Canonical design. Bubble-to-bubble logic. Karnaugh maps and combinational circuit minimization Introduction to VHDL Decoders, encoders, tristate devices, multiplexers, and demultiplexers Implementation of combinational circuits with decoders and multiplexers, comparators, parity circuits, adders-subtractors Bistable elements, latches, and flip-flops Registers, shift registers, and counters Finite state machine design methodology Finite state machine design methodology Finite state machine design examples Error-correcting synchronous sequential circuits (self-correcting counters as examples) Finite state machine design examples ECTS - Workload Table: Activities Number Hours Workload Preparation for Midterm exam 2 15 30 Quiz 7 1 7 Project (including preparation and presentation if applicable) 1 25 25 Preparation for Final exam 1 15 15 Laboratory (including preparation) 14 4 56 Midterm exam 2 2 4 Course hours 14 4 56 Final exam 1 3 3 Total Workload: 196 Total Workload / 30: 196 / 30 6.53 ECTS Credits of the Course: 6,5 Type of Course: Lecture - Laboratory Work - Project Teaching Methods: Lecture - Assignment