Senior design project involving design and implementation of a complete electrical and electronics engineering system. Development involving multiple areas of electrical and electronics engineering. Simulations. Prototype development and testing. Technical communications and teamwork skills enrichment.
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| Dönem | Course CPA | |
|---|---|---|
| 2025-2026 Fall | 3.71 | 1 sec · 8 öğr |
| 2024-2025 Fall | 3.02 | 1 sec · 19 öğr |
| 2024-2025 Spring | 2.53 | 1 sec · 7 öğr |
| 2023-2024 Fall | 2.40 | 1 sec · 14 öğr |
| 2023-2024 Spring | 2.77 | 1 sec · 14 öğr |
| 2022-2023 Fall | 2.38 | 1 sec · 20 öğr |
| 2022-2023 Spring | 2.32 | 1 sec · 23 öğr |
| 2021-2022 Fall | 2.81 | 1 sec · 20 öğr |
| 2021-2022 Spring | 2.29 | 1 sec · 11 öğr |
| 2020-2021 Fall | 2.18 | 1 sec · 18 öğr |
Aggregate course GPA — Bilkent STARS'tan public data. Hoca-bazlı per-section detayı için STARS evaluation report →. Öğrenci anket cevapları KVKK kapsamında defter'de tutulmaz.
Course Learning Outcomes: Course Learning Outcome Assessment Conduct lab experiments in preparation for the term project; demonstrate and report on the results obtained Lab work Develop mathematical models and conduct analysis for complex engineering problems, Quiz Term project Papers(s)/Reports Design and implement a complete electrical and electronics engineering system involving multi-disciplinary work as a team Term project Papers(s)/Reports
1. Students are permitted to use GenAI tools to generate VHDL design and testbench code for assignments. 2. Each group is required to prepare a comprehensive report detailing their use of GenAI throughout the design process. Students shall act as Lead Engineers overseeing the AI. 3. The report must include the initial problem definitions provided to the GenAI, as well as every subsequent prompt, data input, and clarification. The full, unedited chat history must be documented, including "Correct
Lecture: Introduction to EEE491, discussion on the project, requirements. Speech Recognition. Introduction to FPGA, FPGA Design Flow. Lab: Identification of the groups. Introduction to FPGAs. Discussion on system components, presentation of Basys-3 board and “Using the Vivado Design Suit”. All lab assignments. Lecture: Circuit design, Amplifier circuits, Operational Amplifier. Low-pass, high-pass, band-pass filters. Lab: Study of lab assignments. Lecture: Finite-State Machines (FSM), FSM state-transition diagrams. VHDL practice, variable vs. signal assignments. Lab: Study of lab assignments and Lab-DEBUG assignment demonstration Lecture: VHDL practice. Noise on PCB layout, coupling R, L, C. Lab: Study of lab assignments and Lab-ADC assignment demonstration Lecture: VHDL practice on FSM. FPGA Design Implementation. Lab: Study of lab assignments and Lab-WINDOW assignment demonstration Lecture: Quantization, Sampling, Aliasing, A/D conversion, ADC datasheet, SPI interface. Lab: Study of lab assignments. Lecture: Introduction to FFT IP block. Lab: Study of lab assignments and Lab-PCB assignment demonstration Lecture: Configuration of FFT IP block. Lab: Study of lab assignments and Lab-CTRL assignment demonstration Lecture: Linear Time-Invariant Systems, Fast Fourier Transform, Discrete Time Fourier Transform, Discrete Fourier Transform, Spreading of energy (leakage) and time-domain windowing Lab: Study of lab assignments and Lab-FFT assignment demonstration Lecture: Product Development, System Engineering Lab: Study of lab assignments and Lab-MATLAB assignment demonstration tests. Lecture: Process V-model, System Modeling. Lab: Study of lab assignments and Lab-MEL assignment demonstration Lecture: Requirements Engineering, Testing (Verification and Validation) Lab: Study of lab assignments and Lab-DCT assignment demonstration Lecture: Project Management Lab: Study of lab assignments and Lab-COMPARE assignment demonstration Lecture: System on Chip by FPGA, Embedded systems, FPGA SoC architecture examples, FPGA technology Lab: Study of lab assignments. ECTS - Workload Table: Activities Number Hours Workload Laboratory (including preparation) 14 4 56 Report (including preparation and presentation if applicable) 1 20 20 Preparation for Quiz 4 1 4 Quiz 4 1 4 Individual or group work 14 3 42 Project (including preparation and presentation if applicable) 1 40 40 Course hours 14 2 28 Total Workload: 194 Total Workload / 30: 194 / 30 6.47 ECTS Credits of the Course: 6,5 Type of Course: Lecture - Laboratory - Senior Project Course Material: PP - Written Teaching Methods: Lecture - Exercises - Assignment