Introduction to CMOS VLSI Design

This is where digital logic stops being abstract gates and starts being actual silicon — you learn how transistors, parasitics, and layout geometry determine whether a chip is fast, low-power, or even functional. Expect to work through CMOS device equations and logical-effort timing analysis by hand, then move into Cadence to draw schematics and layouts that respect real foundry design rules, culminating in a project. It sits at the bridge between device physics and digital design, and is the standard entry point for anyone heading into VLSI, chip design, or graduate work in integrated circuits.