Number systems, Binary numbers, Logic levels, transistors, gates, Boolean expressions. Combinational logic: Boolean algebra, simplification of Boolean expressions. Logic minimization with Karnaugh maps, don't-care conditions. Introduction to System Verilog. Combinational building blocks, multiplexers, decoders, propagation delays, glitches. Verilog modeling. Sequential logic: SR latch, D-latch, D flip-flop, synchronous sequential circuits. Finite State Machine design, Moore and Mealy models, state encodings, timing of sequential circuits. Verilog modeling of sequential circuits. Signed numbers, Adders, ALU, comparators. Registers, register files. Counters, timers. High level state machines, RTL design, RAM, ROM. FPGA, programmable processors.
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| Dönem | Course CPA | |
|---|---|---|
| 2025-2026 Fall | 2.41 | 6 sec · 148 öğr |
| 2024-2025 Fall | 2.46 | 6 sec · 174 öğr |
| 2024-2025 Spring | 2.33 | 4 sec · 79 öğr |
| 2023-2024 Fall | 2.39 | 6 sec · 164 öğr |
| 2023-2024 Spring | 2.58 | 2 sec · 84 öğr |
| 2022-2023 Fall | 2.46 | 6 sec · 203 öğr |
| 2022-2023 Spring | 1.98 | 2 sec · 63 öğr |
| 2021-2022 Fall | 2.30 | 6 sec · 167 öğr |
| 2021-2022 Spring | 2.58 | 3 sec · 89 öğr |
| 2020-2021 Fall | 2.55 | 6 sec · 184 öğr |
Aggregate course GPA — Bilkent STARS'tan public data. Hoca-bazlı per-section detayı için STARS evaluation report →. Öğrenci anket cevapları KVKK kapsamında defter'de tutulmaz.
1. Weighted average score of the midterm exam and quizzes (2 x midterm_score + avg_quiz_scores)/3: at least 40%. 2. Average score of the labs at least 50%. 3. Absent from no lab (only the tutorial lab can be missed).
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Introduction, digital values, number systems: decimal, binary and hexadecimal Logic gates and physical characteristics, CMOS transistors, power consumption Boolean algebra Boolean equations, canonical forms, Combinational logic, hardware reduction, X and Z logic values, introduction to Verilog Karnaugh maps, MUXes and decoders, Combinational timing & non-ideal behavior, Verilog modelling Latches & flip-flops, basic register, synchronous logic design Finite state machines, encoding, Mealy vs. Moore FSM examples, Verilog modelling Timing, parallelism, Verilog modelling; MIDTERM EXAM Arithmetic functions, adders, subtractors, comparators, shifters, ALU, Verilog models Counters, shift registers, Timers,Verilog models Counters, shift registers, Timers,Verilog models High Level State Machines High Level State Machines Programmable Processors ECTS - Workload Table: Activities Number Hours Workload Project (including preparation and presentation if applicable) 1 25 25 Individual or group work 14 2 28 Course hours 14 3 42 Laboratory (including preparation) 5 12 60 Midterm exam 1 2 2 Preparation for Midterm exam 1 15 15 Preparation for Final exam 1 15 15 Quiz 5 1 5 Presentation (including preparation) 1 1 1 Final exam 1 2 2 Report (including preparation and presentation if applicable) 1 5 5 Total Workload: 200 Total Workload / 30: 200 / 30 6.67 ECTS Credits of the Course: 6,5 Type of Course: Laboratory Work - Lecture Teaching Methods: Lecture