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EEE 414

Introduction to CMOS VLSI Design

Introduction to CMOS circuits, MOS transistor theory, CMOS processing technology, CMOS circuit characterization. CMOS VLSI circuit design, clocking strategies, case studies.

Credit3
ECTS5
BölümElectrical and Electronics Engineering
FacultyFaculty of Engineering
PrereqEEE 313

Hocalar 0 bu dönem · 4 geçmiş

Geçmişte ders veren (4 kişi)
Volkan Kurşun, Burçin Çakır, Abdullah Atalar, Murat Eskiyerli

→ STARS müfredatı / syllabus

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↑ konuya EEE 414 yaz

Geçmiş GPA dağılımı 10 dönem · ort. 2.76

DönemCourse CPA
2023-2024 Fall 2.58 1 sec · 30 öğr
2022-2023 Fall 2.71 1 sec · 7 öğr
2021-2022 Spring 3.12 1 sec · 30 öğr
2020-2021 Spring 3.23 1 sec · 21 öğr
2019-2020 Fall 2.81 1 sec · 20 öğr
2017-2018 Fall 2.60 1 sec · 19 öğr
2015-2016 Fall 2.48 1 sec · 19 öğr
2012-2013 Fall 2.99 1 sec · 17 öğr
2010-2011 Fall 2.30 1 sec · 25 öğr
2008-2009 Fall 2.81 1 sec · 15 öğr

Aggregate course GPA — Bilkent STARS'tan public data. Hoca-bazlı per-section detayı için STARS evaluation report →. Öğrenci anket cevapları KVKK kapsamında defter'de tutulmaz.

Müfredat detayı STARS syllabus

📚 Önerilen kaynaklar

  • Önerilen CMOS VLSI Design: A Circuits and Systems Perspective 4th Edition Neil Weste, David Harris · 2011/Fourth Edition · Pearson
  • Önerilen Digital Integrated Circuits A Design Perspective Jan Rabaey, Anantha Chandrakasan · and Borivoje Nikolic · 2003/Second Edition

⚠️ FZ engelleyen şartlar

Minimum points to qualify for final exam (excluding project and final exam) is 15 out of 45.

📅 Haftalık müfredat

Introduction to Chip Design and Metal-Oxide-Semiconductor Field-Effect Transistors Metal-Oxide-Semiconductor Field-Effect Transistors CMOS Layout and Fabrication CMOS Layout and Fabrication Digital Signals and Noise Margins CMOS Combinational Circuits Part I CMOS Combinational Circuits Part I Power Consumption of Digital Integrated Circuits Performance of CMOS Circuits: The Dynamic Behavior Design for Maximum Speed: Logical Effort Methodology Design for Maximum Speed: Logical Effort Methodology CMOS Combinational Circuits Part II CMOS Combinational Circuits Part II Datapath Operators: Adders ECTS - Workload Table: Activities Number Hours Workload Homework 5 9 45 Preparation for Final exam 1 20 20 Project (including preparation and presentation if applicable) 1 40 40 Course hours 14 3 42 Final exam 1 3 3 Total Workload: 150 Total Workload / 30: 150 / 30 5 ECTS Credits of the Course: 5 Type of Course: Lecture Course Material: Cadence